1. Field of the Invention
The present invention relates to a data processor, more particularly, to a microprocessor which decodes and executes a train of instructions of variable length.
2. Description of the Related Art
A typical microprocessor includes an instruction buffer for storing prefetched instruction codes, and a decoder which receives a train of instructions of variable length fed from the instruction buffer and decodes them to produce control information for data processing (e.g., control information on pipeline control, microprogram addresses, or the like). To decode and execute the train of instructions of variable length, the decoder must receive valid data, i.e., valid instruction codes. To this end, the instruction buffer in the conventional processor predecodes the train of instructions, thereby always to supply the decoder with valid data. At this time, the instruction buffer determines an update quantity of the instruction to be next decoded by the decoder.
However, where the instruction buffer must predecode many bits from among the instruction codes to determine the update quantity of the instructions, the predecoding requires as long a time as that necessary for the decoding of instructions by the decoder. Accordingly, a drawback occurs in that the instruction buffer cannot quickly feed valid instruction codes to the decoder. This leads to a lowering in the data processing speed of the entire processor and thus is not preferable.